Chemical-mechanical polishing (CMP) is a modern technique for planarizing the layer of isolation material that is grown or deposited between active areas of a semiconductor substrate. The term "active area" is commonly used to describe that portion of the semiconductor substrate on which components are built, such as transistors, capacitors and resistors. As is well known in the art, in order to prevent conduction or crosstalk between active areas on a substrate, an electrical isolation material, referred to herein as a refill material, is placed between the active regions. One common method for making space for the refill material, is to etch a trench into the silicon substrate, by methods well known in the art. This space is then filled (refilled) with the isolation material. A common refill material is silicon dioxide.
The top of the refill layer is not planar because of the differences in topography of the surface of the substrate caused by the presence of active areas and some portions of the substrate and not in others. This is clearly illustrated in FIG. 1A in which the semiconductor device 100 being fabricated has reached the stage in which the refill layer has been deposited. In FIG. 1A the substrate 102 has active areas of silicon 104 separated by trenches 112 on the substrate 102. Notice that the trenches between active areas A, B and C are much narrower than the trench between active areas C and D. On top of each of the active areas is an isolation layer 106 which is typically a pad oxide of silicon dioxide. As used herein "isolation layer" refers to a layer which provides electrical and/or physical isolation. On top of the pad oxide 106 is a isolation layer 108, which is typically silicon nitride. Once the trenches have been made, the area between the trenches are filled with refill layer 110, such as silicon dioxide. As can clearly be seen in FIG. 1A, the refill layer does not have a flat topography, but has significant protrusions above the active areas A, B, C and D. Where there are no active areas, such as between active areas C and D, the deposition is relatively flat.
As is well known in the art, it is desirable to have a flat or planarized surface for the refill layer 110 in order that subsequent layers of the semiconductor device be built on a flat surface. In order to achieve this planarized effect, one technique that is commonly used is CMP. FIG. 1B shows the results of device 100 after CMP. Layer 114 is layer 110 after it has been planarized by the CMP operation. The CMP operation stops when it reaches the silicon nitride 108 thus leaving the refill layer 114 slightly below the top of the silicon nitride layer 108. This can be clearly be seen in the areas between active layers A and B and active layers B and C. However, where there is a significant distance between active areas, such as between active areas C and D, the refill layer 114 is overpolished causing significant "dishing" 116 which results in a non-planarized surface. More significantly, active area D has been overpolished to the extent that the silicon nitride layer 108, the silicon dioxide layer 106 has been completely polished away and a portion of the active area silicon 104 has been polished away. The overpolishing will impair device performance, reliability and yield. It is believed that the overpolishing for active area D is caused by the unevenness in pressure that is applied because of the difference in the area density between the area encompassing active areas A, B, and C and the area which only has active area D. The term "area density" refers to the percentage of any portion of the substrate that contains active area, in contrast to refill material or trench.
FIG. 1C shows a TEM cross section of an active area after nitride strip. The active silicon area is covered by a delineating polycrystalline silicon layer which has been deposited on the surface which is in turn covered by a silicon nitride area which appears as a dark black line. It can clearly be seen from this figure that there is damage and trenching into the active silicon area. In contrast, the photograph in FIG. 1D shows a similar area in which no damage has occurred. Note the presence of the pad oxide which appears as a thin white line between the active silicon and the delineating polycrystalline silicon layer which shows that there has been no silicon exposure during the CMP.
Accordingly, there is a need for a low-cost and effective method for reducing such overpolishing.